Semiconductor chips typically are connected to external circuitry through contacts on a surface of the chip. The contacts on the chip typically are disposed in patterns such as an area array which substantially covers the front surface of the chip, or in elongated rows extending parallel to and adjacent each edge of the chip front surface. Each contact on the chip must be connected to external circuitry, such as the circuitry of a supporting substrate or circuit panel. Various processes for making these interconnections use prefabricated arrays of leads or discrete wires. For example, in the tape automated bonding ("TAB") process, a dielectric film, such as a thin foil of polyimide is provided with one or more bond windows. An array of terminals are provided on one surface of the dielectric film and leads connected to the terminals extend outwardly from a central portion of the dielectric film and overlie the bond windows. The dielectric film is juxtaposed with a semiconductor chip so that the bond windows are aligned with the chip and so that the outermost ends of the leads will extend over the contact bearing face on the chip. The outermost ends of the leads are then bonded to the contacts of the chip, as by ultrasonic or thermocompression bonding which in turn connects the contacts with terminals on the dielectric film. The chip is then connected to an external circuit element by connecting the terminals to contact pads on the external circuit element.
Commonly assigned International Application No. PCT/US93/06930 filed Jul. 23, 1993, the disclosure of which is incorporated herein by reference, discloses another connection component for a semiconductor chip. The connection component includes a support structure formed from dielectric materials such as polymeric materials. The support structure has a top surface and a bottom surface, a central portion, a peripheral portion and gaps extending from the top surface to the bottom surface of the support structure and between the central portion and the peripheral portion thereof. Each gap in the support structure may be formed as an elongated slot. The support structure also includes terminals on the central portion and leads having first ends connected to the terminals and second ends extending over the slots. The second ends of the leads are connected by a frangible section to an elongated bus extending over the peripheral portion of the support structure alongside each elongated slot. The bus reinforces the support structure and the leads when the component is assembled to a semiconductor chip. The bus is provided alongside each slot on the peripheral portion so that one such bus extends alongside each slot. The slots are connected to one another to form a substantially continuous channel surrounding the central portion, leaving the central portion connected to the peripheral portion only through the leads. During the connection process, the frangible sections of the leads are broken so that the leads are detached from the peripheral portion, thereby detaching the central portion from the peripheral portion and leaving the central portion connected to the chip. The terminals on the support structure are then connected to an external circuit element for electrically interconnecting the semiconductor chip to the external circuit element.
Certain designs have been found to improve the performance of chip packages comprising semiconductor chips and connection components. These designs reduce the amount of stress on the electrical components within the package by redistributing the thermal cycling stress into a portion of the chip package itself. An example of such a design is shown in U.S. Pat. Nos. 5,148,265 and 5,148,266, both disclosures of which are incorporated herein by reference. One disclosed embodiment of these patents shows the use of a connection component in combination with a compliant layer to reduce problems associated with thermal cycling. Typically, the compliant layer includes an elastomeric layer which, in the finished package, is disposed between the connection component and the contact bearing surface of the chip. The compliant layer provides resiliency to individual terminals on the connection component, allowing each terminal to move in relation to its electrically connected chip contact to accommodate thermal cycling as necessary during testing, final assembly and thermal cycling of the device.
It has also been found desirable to introduce encapsulating material between and/or around elements of the semiconductor packages in an effort to reduce and/or redistribute the strain and stress on the connections between the semiconductor chip and an external circuit element during operation of the chip, and to seal the elements against corrosion, as well as to insure intimate contact between the encapsulant, the semiconductor chip and the other elements of the chip package.
Thus, despite the substantial time and effort devoted heretofore to the problems associated with mounting and connecting semiconductor chips to external elements, there have still been substantial, unmet needs for improvements in such processes and in the equipment and components used to practice the same.